Dynamic voltage frequency scaling (DVFS) technique has been known as a technique for reducing electric power of a processor. The DVFS technique is a technique that raises or lowers an operating voltage depending on a load of the processor. The operating voltage is raised in a case where the load of the processor is high to increase a clock frequency of the processor, thereby obtaining high-speed processing. On the other hand, the voltage is lowered in a case where the load thereof is low to decrease the clock frequency, thereby reducing electric power consumption.
It has been known that, when the DVFS technique is applied to a memory circuit such as a dynamic random access memory (DRAM) or a magnetoresistive RAM (MRAM) to link a voltage supplied to the memory circuit to a voltage supplied to the processor, there is a risk of reducing an operating margin or causing a defective operation. In order to avoid this problem, an approach is also employed that a voltage supplied to a processor core is raised or lowered depending on the load using the DVFS technique, while a voltage supplied to the memory circuit is kept constant regardless of the degree of the load.
A write voltage of the MRAM is known to abruptly rise in a case where a write time is shortened. As described above, in a case where the write voltage to the MRAM is set so as to be always constant regardless of an operating state of an arithmetic core, the write voltage is always kept raised in accordance with the arithmetic core in a high-load state, Consequently, the write voltage remains high even after the arithmetic core has shifted to a light-load state, resulting in an increase in the electric power consumption of the MRAM.